1. Field of the Invention
The present invention generally relates to a bit line sense amplifier control circuit of a semiconductor memory device, and more specifically, to a technology of removing an overdriving period at a refresh mode, thereby reducing current consumption at a self-refresh mode.
2. Description of the Related Art
Generally, a bit line sense amplifier senses and amplifies data on a bit line to output the data to a data bus, and a data bus sense amplifier re-senses and re-amplifies the data amplified by the bit line sense amplifier to output the data to a data output buffer.
The operation of the general bit line sense amplifier is described as follows. Here, a cross coupled latch type amplifier is exemplified for the bit line sense amplifier.
First, a bit line is precharged to a precharge voltage (for example, half of an internal power voltage VDD). Here, two bit lines are equalized to remove a voltage difference between one bit line connected to a selected memory cell and another bit line which is not connected to the selected memory cell.
A row decoder decodes an externally inputted row address to select a word line corresponding to the row address.
Then, a cell transistor connected to the selected word line is turned on.
As a result, a potential difference is generated between one bit line connected to a selected memory cell and another bit line which is not connected to the selected memory cell by charge sharing between cell capacitance and bit line capacitance.
Here, when sense amplifier control signals RTO and SB are enabled, the sense amplifier control signal RTO becomes at a high level VDD, and the sense amplifier control signal SB becomes at a low level VSS. As a result, a bit line sense amplifier is operated to amplify the potential difference between the bit line connected to the selected memory cell and another bit line which is not connected to the selected memory cell.
For example, suppose that data stored in the selected memory cell is low level data. A potential of the bit line connected to the selected memory cell becomes lower than that of a precharge voltage, and a potential of the bit line which is not connected to the selected memory cell is maintained at that of the precharge voltage, so that a potential difference occurs between the two bit lines.
Therefore, the bit line sense amplifier which is a cross coupled latch type amplifier sets the bit line connected to the selected memory cell at the low level VSS by the low level bit line sense amplifier control signal SB, and sets the bit line which is not connected to the selected cell at the high level VDD by the high level bit line sense amplifier control signal RTO.
Thereafter, a column address is decoded by a column decoder. When a column control signal YI corresponding to the column address is enabled to a high level, data on the bit line is amplified by the bit line sense amplifier and transmitted into a data bus.
The control signal RTO for driving the bit line sense amplifier is driven as an external power voltage VEXT at the initial amplification operation in order to improve an operating speed of the bit line sense amplifier, thereby reducing a skew. At a normal mode, the control signal RTO is driven to an internal power voltage (core voltage) VCORE or an internal circuit supply voltage VPERI.
In case of a low power semiconductor memory device, a method for reducing current consumption is more preferably used than a method for improving an operating speed at a self-refresh mode. However, the current consumption is increased. because the bit line sense amplifier control signal RTO is driven to the external power voltage VEXT higher than the internal power voltage VCORE which is a target voltage for an overdriving period.